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Digital design 5th edition mano digital design morris mano fifth general chemistry 10th edition petrucci solution manual of digital logic and digital logic design by morris manoDigital Design 5e Solution DocsityDigital Design Morris Mano 3rd Edition Livro De Sistemas
Digital Design 5th Edition Mano Solutions Manual - Free download as PDF File (.pdf), Text File (.txt) or read online for free. Download full file at https. SOLUTIONS MANUAL DIGITAL. AN INTRODUCTION TO THE VERILOG HDL. Professor Emeritus California State University, Los Angeles. Professor Emeritus University of Colorado, Colorado Springs. Rev 02/14 / CHAPTER 1. Solutions Manual comes in a PDF or Word format and available for download only. Mano Digital Design 5th Edition Solutions Manual only NO Test Bank included on this purchase. If you want the Test Bank please search on the search box. All orders are placed anonymously.Digital Design 2nd Edition Morris Mano Solution ManualSolution Manual Of Digital Logic And Puter Design 2nd EditionDigital Design Morris Mano 3rd Edition Livro De SistemasDigital Design 5th Edition Mano Solutions Manual 6ngeq8j76klvDigital Design 5th Edition Mano Solutions Manual StudocuDigital Design 5th Edition Mano Solutions Manual StudocuDigital Design Morris Mano 4th Edition Solution Manual Et 2Digital Design 5th Edition Mano Solutions Manual StudocuDigital Design Fifth Edition Solution Manual 5thDigital Design 5th Edition Mano Solutions Manual StudocuSolutions C1 1 Manual Digital Design With AnDigital Design 5th Edition Mano Solutions Manual StudocuSolution Manual Of Digital Logic And Puter Design 2nd Edition
Solution manual of digital logic and puter design 2nd edition digital design morris mano fifth edition بوکت digital design morris mano fifth edition بوکت digital design 5th edition m morris man film general chemistry 10th edition petrucci solutionDigital Design Fifth Edition Solutions ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual SOLUTIONS MANUAL DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs rev 02/14/2012 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual1 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual CHAPTER 1 1.1Base-10: Octal: Hex: Base-1216 17 20 21 10 11 14 151.2(a) 32,76818 22 12 1619 23 13 1720 24 14 1821 25 15 19(b) 67,108,864 322 23 24 25 26 27 30 31 16 17 18 19 1A 1B 20 2126 27 28 29 30 32 33 34 35 36 1A 1B 1C 1D 1E 22 23 24 25 2631 37 1F 2732 40 20 28(c) 6,871,947,674(4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 580101.32(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010 1.41.5(435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510 (345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 216 -1 = 65,53510 Hexadecimal equivalent: FFFF16 Let b = base (a) 14/2 = (b + 4)/2 = 5, so b = 6 (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8 (c) (2 *b + 4) + (b + 7) = 4b, so b = 111.6(x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22 Therefore: 6 + 3 = b + 1m, so b = 8 Also, 6*3 = (18)10 = (22)8 1.764CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )81.8(a) Results of repeated division by 2 (quotients are followed by remainders): 43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) Answer: 1111_10102 = FA163(0)1(1)(b) Results of repeated division by 16: 43110 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9(a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual2 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125 1.10(a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310 (b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510 1.11Reason: 110.0102 is the same as 1.100102 shifted to the left by two places. 1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 1110112 / 1012 = 5910 / 510 ≅ 1011.112 = 58.75101.12(a) 10000 and 110111 1011 +101 10000 = 16101011 x101 1011 1011 110111 = 5510(b) 62h and 958h 2Eh +34 h 62h1.13 0010_1110 0011_0100 0110_0010 = 98102Eh x34h B 38 2 8A 9 5 8h = 239210(a) Convert 27.315 to binary:27/2 = 13/2 6/2 3/2 ½Integer Quotient 13 6 3 1 0Remainder + + + + +½ ½ 0 ½ ½Coefficient a0 = 1 a1 = 1 a2 = 0 a3 = 1 a4 = 1Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual3 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 2710 = 110112 .315 x 2 .630 x 2 .26 x 2 .52 x 2= = = =Integer 0 1 0 1+ + + +Fraction .630 .26 .52 .04Coefficient a-1 = 0 a-2 = 1 a-3 = 0 a-4 = 1.31510 ≅ .01012 = .25 + .0625 = .3125 27.315 ≅ 11011.01012 (b) 2/3 ≅ .6666666667 .6666_6666_67 x 2 .3333333334 x 2 .6666666668 x 2 .3333333336 x 2 .6666666672 x 2 .3333333344 x 2 .6666666688 x 2 .3333333376 x 2Integer = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0+ + + + + + + +Fraction .3333_3333_34 .6666666668 .3333333336 .6666666672 .3333333344 .6666666688 .3333333376 .6666666752Coefficient a-1 = 1 a-2 = 0 a-3 = 1 a-4 = 0 a-5 = 1 a-6 = 0 a-7 = 1 a-8 = 0.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110 .101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)). 1.14` 1.15(a)0001_0000 1s comp: 1110_1111 2s comp: 1111_0000(b)0000_0000 1s comp: 1111_1111 2s comp: 0000_0000(c)1101_1010 1s comp: 0010_0101 2s comp: 0010_0110(d)1010_1010 1s comp: 0101_0101 2s comp: 0101_0110(e)1000_0101 1s comp: 0111_1010 2s comp: 0111_1011(f)1111_1111 1s comp: 0000_0000 2s comp: 0000_0001(a)25,478,036 9s comp: 74,521,963 10s comp: 74,521,964(b)63,325,600 9s comp: 36,674,399 10s comp: 36,674,400(c)25,000,000 9s comp: 74,999,999 10s comp: 75,000,000(d)00000000 9s comp: 99999999 10s comp: 100000000 1.16 15s comp: 16s comp: 1.17C3DF 3C20 3C21C3DF: 1100_0011_1101_1111 1s comp: 0011_1100_0010_0000 2s comp: 0011_1100_0010_0001 = 3C21(a) 2,579 → 02,579 →97,420 (9s comp) → 97,421 (10s comp) 4637 – 2,579 = 2,579 + 97,421 = 205810 (b) 1800 → 01800 → 98199 (9s comp) → 98200 (10 comp) 125 – 1800 = 00125 + 98200 = 98325 (negative) Magnitude: 1675 Result: 125 – 1800 = 1675Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual4 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.181.19Note: Consider sign extension with 2s complement arithmetic. (a)0_10010 (b) 0_100110 1s comp: 1_01101 1s comp: 1_011001 with sign extension 2s comp: 1_01110 2s comp: 1_011010 0_10011 0_100010 Diff: 0_00001 (Positive) 1_111100 sign bit indicates that the result is negative Check:19-18 = +1 0_000011 1s complement 0_000100 2s complement 000100 magnitude Result: -4 Check: 34 -38 = -4(c)0_110101 (d) 1s comp: 1_001010 1s comp: 2s comp: 1_001011 2s comp: 0_001001 Diff: 1_010100 (negative) 0_101011 (1s comp) 0_101100 (2s complement) 101100 (magnitude) -4410 (result)0_010101 1_101010 with sign extension 1_101011 0_101000 0_010011 sign bit indicates that the result is positive Result: 1910 Check: 40 – 21 = 1910+9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20+49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001→ 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual5 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 7810 Result: (-29) + (-49) = -7810 1.21+9742 → 009742 → 990257 (9’s comp) → 990258 (10s) comp +641 → 000641 → 999358 (9’s comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b) (+9742) + (-641) →009742 + 999359 = 009102 Result: (+9742) + (-641) = 9102 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -103831.226,514 BCD: ASCII: ASCII:0110_0101_0001_0100 0_011_0110_0_011_0101_1_011_0001_1_011_0100 0011_0110_0011_0101_1011_0001_1011_01001.23 0111 0110 1101 0110 0001 0011 0001 0001 0001 0100 1.24 0001 ( 791) 1000 (+658) 100101001001 (1,449)(a)6 0 0 0 0 0 0 1 1 1 1 1.251001 0101 1110 0110 01003 0 0 0 1 1 1 0 0 0 1(b)1 0 0 1 0 1 1 0 1 1 01 0 1 0 0 0 1 0 0 1 0Decimal 0 1 2 3 4 (or 0101) 5 6 7 (or 1001) 8 96 0 0 0 0 0 0 1 1 1 14 0 0 0 0 1 1 0 0 0 02 0 0 1 1 0 0 0 0 1 11 0 1 0 1 0 1 0 1 0 1Decimal 0 1 2 3 4 5 6 (or 0110) 7 8 9(a) 6,24810 (b)BCD: 0110_0010_0100_1000 Excess-3: 1001_0101_0111_1011(c) (d)2421: 6311:0110_0010_0100_1110 1000_0010_0110_1011 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual6 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 1.266,248 9s Comp: 2421 code: 1s comp c: 6,2482421 1s comp c3,751 0011_0111_0101_0001 1001_1101_1011_0001 (2421 code alternative #1) 0110_0010_0100_1110 (2421 code alternative #2) 1001_1101_1011_0001 MatchDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual7 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb’s select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the ’number’ of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.)1.27 1.28G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_111001011.29Steve Jobs1.30 73 F4 E5 76 E5 4A EF 62 73 73: F4: E5: 76: E5: 4A: EF: 62: 73:0_111_0011 1_111_0100 1_110_0101 0_111_0110 1_110_0101 0_100_1010 1_110_1111 0_110_0010 0_111_0011s t e v e j o b s 1.3162 + 32 = 94 printing characters1.32bit 6 from the right1.33(a) 8971.34ASCII for decimal digits with even parity: 1.358 (b) 564(0): 00110000 (4): 10110100 (8): 10111000 (1): (5): (9): (c) 87110110001 00110101 00111001 (d) 2,199(2): (6): 10110010 00110110 (3): (7): 00110011 10110111 (a) a b c a fb cgf g1.36 ab a fgbf g Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 9 CHAPTER 2 2.1(a) xyzx+y+z000 001 010 011 100 101 110 1110 1 1 1 1 1 1 1(x + y + z)’ x’ 1 0 0 0 0 0 0 01 1 1 1 0 0 0 0y’z’x’ y’ z’xyz(xyz)(xyz)’x’y’z’x’ + y’ + z’1 1 0 0 1 1 0 01 0 1 0 1 0 1 01 0 0 0 0 0 0 0000 001 010 011 100 101 110 1110 0 0 0 0 0 0 11 1 1 1 1 1 1 01 1 1 1 0 0 0 01 1 0 0 1 1 0 01 0 1 0 1 0 1 01 1 1 1 1 1 1 0(b)(c) xyzx + yz(x + y)(x + z)(x + y)(x + z)xyzx(y + z)xyxzxy + xz000 001 010 011 100 101 110 1110 0 0 1 1 1 1 10 0 1 1 1 1 1 10 1 0 1 1 1 1 10 0 0 1 1 1 1 1000 001 010 011 100 101 110 1110 0 0 0 0 1 1 10 0 0 0 0 0 1 10 0 0 0 0 1 0 10 0 0 0 0 1 1 1(c)(d) xyzxy+zx + (y + z)(x + y)(x + y) + zxyzyzx(yz)xy000 001 010 011 100 101 110 1110 0 0 0 1 1 1 10 1 1 1 0 1 1 10 1 1 1 1 1 1 10 0 1 1 1 1 1 10 1 1 1 1 1 1 1000 001 010 011 100 101 110 1110 0 0 1 0 0 0 10 0 0 0 0 0 0 10 0 0 0 0 0 1 1 2.2(xy)z 0 0 0 0 0 0 0 1 (a) xy + xy’ = x(y + y’) = x (b) (x + y)(x + y’) = x + yy’ = x(x +y’) + y(x + y’) = xx + xy’ + xy + yy’ = x (c) xyz + x’y + xyz’ = xy(z + z’) + x’y = xy + x’y = y (d) (A + B)’(A’ + B’)’ = (A’B’)(A B) = (A’B’)(BA) = A’(B’B)A = 0 (e) (a + b + c’)(a’b’ + c) = aa’b’ + ac + ba’b’ + bc + c’a’b’ + c’c = ac + bc +a’b’c’ (f) a’bc + abc’ + abc + a’bc’ = a’b(c + c’) + ab(c + c’) = a’b + ab = (a’ + a)b = b 2.3(a) ABC + A’B + ABC’ = AB + A’B = BDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 10 (b) x’yz + xz = (x’y + x)z = z(x + x’)(x + y) = z(x + y) (c) (x + y)’(x’ + y’) = x’y’(x’ + y’) = x’y’ (d) xy + x(wz + wz’) = x(y +wz + wz’) = x(w + y) (e) (BC’ + A’D)(AB’ + CD’) = BC’AB’ + BC’CD’ + A’DAB’ + A’DCD’ = 0 (f) (a’ + c’)(a + b’ + c’) = a’a + a’b’ + a’c’ + c’a + c’b’ + c’c’ = a’b’ + a’c’ + ac’ + b’c’ = c’ + b’(a’ + c’) = c’ + b’c’ + a’b’ = c’ + a’b’ 2.4(a) A’C’ + ABC + AC’ = C’ + ABC = (C + C’)(C’ + AB) = AB + C’ (b) (x’y’ + z)’ + z + xy + wz = (x’y’)’z’ + z + xy + wz =[ (x + y)z’ + z] + xy + wz = = (z + z’)(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z (c) A’B(D’ + C’D) + B(A + A’CD) = B(A’D’ + A’C’D + A + A’CD) = B(A’D’ + A + A’D(C + C’) = B(A + A’(D’ + D)) = B(A + A’) = B (d) (A’ + C)(A’ + C’)(A + B + C’D) = (A’ + CC’)(A + B + C’D) = A’(A + B + C’D) = AA’ + A’B + A’C’D = A’(B + C’D) (e) ABC’D + A’BD + ABCD = AB(C + C’)D + A’BD = ABD + A’BD = BD 2.5(a) xyFsimplifiedF (b) xy FsimplifiedF(c)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual xyz FsimplifiedF(d) AB0 FsimplifiedF(e) xyz FsimplifiedF(f)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual11 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual xyzFFsimplified2.6(a) ABCFFsimplified(b) xyzFFsimplified(c) xyFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual12 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (d) wxyzFFsimplified(e) ABCD Fsimplified = 0F(f) wxyzFFsimplified2.7(a) ABCDFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual13 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (b) wxyzFFsimplified(c) ABCDFFsimplified(d) ABCDFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual14 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (e) ABCDFFsimplified 2.8 F’ = (wx + yz)’ = (wx)’(yz)’ = (w’ + x’)(y’ + z’) FF’ = wx(w’ + x’)(y’ + z’) + yz(w’ + x’)(y’ + z’) = 0 F + F’ = wx + yz + (wx + yz)’ = A + A’ = 1 with A = wx + yz 2.9(a) F’ = (xy’ + x’y)’ = (xy’)’(x’y)’ = (x’ + y)(x + y’) = xy + x’y’ (b) F’ = [(a + c) (a + b’)(a’ + b + c’)]’ = (a + c)’ + (a + b’)’ + (a’ + b + c’)’ =a’c’ + a’b + ab’c (c) F’ = [z + z’(v’w + xy)]’ = z’[z’(v’w + xy)]’ = z’[z’v’w + xyz’]’ = z’[(z’v’w)’(xyz’)’] = z’[(z + v + w’) +( x’ + y’ + z)] = z’z + z’v + z’w’ + z’x’ + z’y’ +z’ z = z’(v + w’ + x’ + y’) 2.10 2.11(a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i) (b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j (a) F(x, y, z) = Σ(1, 4, 5, 6, 7) (b) F(a, b, c) = Σ(0, 2, 3, 7) F = xy + xy’ + y’z 2.12F = bc + a’c’xyzFabcF000 001 010 011 100 101 110 1110 1 0 0 1 1 1 1000 001 010 011 100 101 110 1111 0 1 1 0 0 0 1A = 1011_0001 B = 1010_1100Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual15 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (a) (b) (c) (d) (e) 2.13A AND B = 1010_0000 A OR B = 1011_1101 A XOR B = 0001_1101 NOT A = 0100_1110 NOT B = 0101_0011(a) uxyz(u + x’) Y = [(u + x’)(y’ + z)] (y’ + z)(b) u x yx Y = (u xor y)’ + x (u xor y)’(c) uxy z(u’+ x’) Y = (u’+ x’)(y + z’) (y + z’)(d) u x yzu(x xor z) Y = u(x xor z) + y’y’ (e) u x y zu yzY = u + yz +uxyuxy(f)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual16 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual u xyY = u + x + x’(u + y’) x’(u + y’) (u + y’)2.14(a) xyzF =xy + x’y’ + y’z(b) xyzF = xy + x’y’ + y’z = (x’ + y’)’ + (x + y)’ + (y + z
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Digital Design 5th Edition Mano Solutions Manual - Free download as PDF File (.pdf), Text File (.txt) or read online for free. Download full file at https. SOLUTIONS MANUAL DIGITAL. AN INTRODUCTION TO THE VERILOG HDL. Professor Emeritus California State University, Los Angeles. Professor Emeritus University of Colorado, Colorado Springs. Rev 02/14 / CHAPTER 1. Solutions Manual comes in a PDF or Word format and available for download only. Mano Digital Design 5th Edition Solutions Manual only NO Test Bank included on this purchase. If you want the Test Bank please search on the search box. All orders are placed anonymously.Digital Design 2nd Edition Morris Mano Solution ManualSolution Manual Of Digital Logic And Puter Design 2nd EditionDigital Design Morris Mano 3rd Edition Livro De SistemasDigital Design 5th Edition Mano Solutions Manual 6ngeq8j76klvDigital Design 5th Edition Mano Solutions Manual StudocuDigital Design 5th Edition Mano Solutions Manual StudocuDigital Design Morris Mano 4th Edition Solution Manual Et 2Digital Design 5th Edition Mano Solutions Manual StudocuDigital Design Fifth Edition Solution Manual 5thDigital Design 5th Edition Mano Solutions Manual StudocuSolutions C1 1 Manual Digital Design With AnDigital Design 5th Edition Mano Solutions Manual StudocuSolution Manual Of Digital Logic And Puter Design 2nd Edition
Solution manual of digital logic and puter design 2nd edition digital design morris mano fifth edition بوکت digital design morris mano fifth edition بوکت digital design 5th edition m morris man film general chemistry 10th edition petrucci solutionDigital Design Fifth Edition Solutions ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual SOLUTIONS MANUAL DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs rev 02/14/2012 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual1 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual CHAPTER 1 1.1Base-10: Octal: Hex: Base-1216 17 20 21 10 11 14 151.2(a) 32,76818 22 12 1619 23 13 1720 24 14 1821 25 15 19(b) 67,108,864 322 23 24 25 26 27 30 31 16 17 18 19 1A 1B 20 2126 27 28 29 30 32 33 34 35 36 1A 1B 1C 1D 1E 22 23 24 25 2631 37 1F 2732 40 20 28(c) 6,871,947,674(4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 580101.32(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010 1.41.5(435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510 (345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 216 -1 = 65,53510 Hexadecimal equivalent: FFFF16 Let b = base (a) 14/2 = (b + 4)/2 = 5, so b = 6 (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8 (c) (2 *b + 4) + (b + 7) = 4b, so b = 111.6(x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22 Therefore: 6 + 3 = b + 1m, so b = 8 Also, 6*3 = (18)10 = (22)8 1.764CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )81.8(a) Results of repeated division by 2 (quotients are followed by remainders): 43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) Answer: 1111_10102 = FA163(0)1(1)(b) Results of repeated division by 16: 43110 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9(a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual2 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125 1.10(a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310 (b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510 1.11Reason: 110.0102 is the same as 1.100102 shifted to the left by two places. 1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 1110112 / 1012 = 5910 / 510 ≅ 1011.112 = 58.75101.12(a) 10000 and 110111 1011 +101 10000 = 16101011 x101 1011 1011 110111 = 5510(b) 62h and 958h 2Eh +34 h 62h1.13 0010_1110 0011_0100 0110_0010 = 98102Eh x34h B 38 2 8A 9 5 8h = 239210(a) Convert 27.315 to binary:27/2 = 13/2 6/2 3/2 ½Integer Quotient 13 6 3 1 0Remainder + + + + +½ ½ 0 ½ ½Coefficient a0 = 1 a1 = 1 a2 = 0 a3 = 1 a4 = 1Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual3 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 2710 = 110112 .315 x 2 .630 x 2 .26 x 2 .52 x 2= = = =Integer 0 1 0 1+ + + +Fraction .630 .26 .52 .04Coefficient a-1 = 0 a-2 = 1 a-3 = 0 a-4 = 1.31510 ≅ .01012 = .25 + .0625 = .3125 27.315 ≅ 11011.01012 (b) 2/3 ≅ .6666666667 .6666_6666_67 x 2 .3333333334 x 2 .6666666668 x 2 .3333333336 x 2 .6666666672 x 2 .3333333344 x 2 .6666666688 x 2 .3333333376 x 2Integer = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0+ + + + + + + +Fraction .3333_3333_34 .6666666668 .3333333336 .6666666672 .3333333344 .6666666688 .3333333376 .6666666752Coefficient a-1 = 1 a-2 = 0 a-3 = 1 a-4 = 0 a-5 = 1 a-6 = 0 a-7 = 1 a-8 = 0.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110 .101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)). 1.14` 1.15(a)0001_0000 1s comp: 1110_1111 2s comp: 1111_0000(b)0000_0000 1s comp: 1111_1111 2s comp: 0000_0000(c)1101_1010 1s comp: 0010_0101 2s comp: 0010_0110(d)1010_1010 1s comp: 0101_0101 2s comp: 0101_0110(e)1000_0101 1s comp: 0111_1010 2s comp: 0111_1011(f)1111_1111 1s comp: 0000_0000 2s comp: 0000_0001(a)25,478,036 9s comp: 74,521,963 10s comp: 74,521,964(b)63,325,600 9s comp: 36,674,399 10s comp: 36,674,400(c)25,000,000 9s comp: 74,999,999 10s comp: 75,000,000(d)00000000 9s comp: 99999999 10s comp: 100000000 1.16 15s comp: 16s comp: 1.17C3DF 3C20 3C21C3DF: 1100_0011_1101_1111 1s comp: 0011_1100_0010_0000 2s comp: 0011_1100_0010_0001 = 3C21(a) 2,579 → 02,579 →97,420 (9s comp) → 97,421 (10s comp) 4637 – 2,579 = 2,579 + 97,421 = 205810 (b) 1800 → 01800 → 98199 (9s comp) → 98200 (10 comp) 125 – 1800 = 00125 + 98200 = 98325 (negative) Magnitude: 1675 Result: 125 – 1800 = 1675Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual4 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.181.19Note: Consider sign extension with 2s complement arithmetic. (a)0_10010 (b) 0_100110 1s comp: 1_01101 1s comp: 1_011001 with sign extension 2s comp: 1_01110 2s comp: 1_011010 0_10011 0_100010 Diff: 0_00001 (Positive) 1_111100 sign bit indicates that the result is negative Check:19-18 = +1 0_000011 1s complement 0_000100 2s complement 000100 magnitude Result: -4 Check: 34 -38 = -4(c)0_110101 (d) 1s comp: 1_001010 1s comp: 2s comp: 1_001011 2s comp: 0_001001 Diff: 1_010100 (negative) 0_101011 (1s comp) 0_101100 (2s complement) 101100 (magnitude) -4410 (result)0_010101 1_101010 with sign extension 1_101011 0_101000 0_010011 sign bit indicates that the result is positive Result: 1910 Check: 40 – 21 = 1910+9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20+49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001→ 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual5 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 7810 Result: (-29) + (-49) = -7810 1.21+9742 → 009742 → 990257 (9’s comp) → 990258 (10s) comp +641 → 000641 → 999358 (9’s comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b) (+9742) + (-641) →009742 + 999359 = 009102 Result: (+9742) + (-641) = 9102 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -103831.226,514 BCD: ASCII: ASCII:0110_0101_0001_0100 0_011_0110_0_011_0101_1_011_0001_1_011_0100 0011_0110_0011_0101_1011_0001_1011_01001.23 0111 0110 1101 0110 0001 0011 0001 0001 0001 0100 1.24 0001 ( 791) 1000 (+658) 100101001001 (1,449)(a)6 0 0 0 0 0 0 1 1 1 1 1.251001 0101 1110 0110 01003 0 0 0 1 1 1 0 0 0 1(b)1 0 0 1 0 1 1 0 1 1 01 0 1 0 0 0 1 0 0 1 0Decimal 0 1 2 3 4 (or 0101) 5 6 7 (or 1001) 8 96 0 0 0 0 0 0 1 1 1 14 0 0 0 0 1 1 0 0 0 02 0 0 1 1 0 0 0 0 1 11 0 1 0 1 0 1 0 1 0 1Decimal 0 1 2 3 4 5 6 (or 0110) 7 8 9(a) 6,24810 (b)BCD: 0110_0010_0100_1000 Excess-3: 1001_0101_0111_1011(c) (d)2421: 6311:0110_0010_0100_1110 1000_0010_0110_1011 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual6 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 1.266,248 9s Comp: 2421 code: 1s comp c: 6,2482421 1s comp c3,751 0011_0111_0101_0001 1001_1101_1011_0001 (2421 code alternative #1) 0110_0010_0100_1110 (2421 code alternative #2) 1001_1101_1011_0001 MatchDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual7 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb’s select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the ’number’ of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.)1.27 1.28G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_111001011.29Steve Jobs1.30 73 F4 E5 76 E5 4A EF 62 73 73: F4: E5: 76: E5: 4A: EF: 62: 73:0_111_0011 1_111_0100 1_110_0101 0_111_0110 1_110_0101 0_100_1010 1_110_1111 0_110_0010 0_111_0011s t e v e j o b s 1.3162 + 32 = 94 printing characters1.32bit 6 from the right1.33(a) 8971.34ASCII for decimal digits with even parity: 1.358 (b) 564(0): 00110000 (4): 10110100 (8): 10111000 (1): (5): (9): (c) 87110110001 00110101 00111001 (d) 2,199(2): (6): 10110010 00110110 (3): (7): 00110011 10110111 (a) a b c a fb cgf g1.36 ab a fgbf g Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 9 CHAPTER 2 2.1(a) xyzx+y+z000 001 010 011 100 101 110 1110 1 1 1 1 1 1 1(x + y + z)’ x’ 1 0 0 0 0 0 0 01 1 1 1 0 0 0 0y’z’x’ y’ z’xyz(xyz)(xyz)’x’y’z’x’ + y’ + z’1 1 0 0 1 1 0 01 0 1 0 1 0 1 01 0 0 0 0 0 0 0000 001 010 011 100 101 110 1110 0 0 0 0 0 0 11 1 1 1 1 1 1 01 1 1 1 0 0 0 01 1 0 0 1 1 0 01 0 1 0 1 0 1 01 1 1 1 1 1 1 0(b)(c) xyzx + yz(x + y)(x + z)(x + y)(x + z)xyzx(y + z)xyxzxy + xz000 001 010 011 100 101 110 1110 0 0 1 1 1 1 10 0 1 1 1 1 1 10 1 0 1 1 1 1 10 0 0 1 1 1 1 1000 001 010 011 100 101 110 1110 0 0 0 0 1 1 10 0 0 0 0 0 1 10 0 0 0 0 1 0 10 0 0 0 0 1 1 1(c)(d) xyzxy+zx + (y + z)(x + y)(x + y) + zxyzyzx(yz)xy000 001 010 011 100 101 110 1110 0 0 0 1 1 1 10 1 1 1 0 1 1 10 1 1 1 1 1 1 10 0 1 1 1 1 1 10 1 1 1 1 1 1 1000 001 010 011 100 101 110 1110 0 0 1 0 0 0 10 0 0 0 0 0 0 10 0 0 0 0 0 1 1 2.2(xy)z 0 0 0 0 0 0 0 1 (a) xy + xy’ = x(y + y’) = x (b) (x + y)(x + y’) = x + yy’ = x(x +y’) + y(x + y’) = xx + xy’ + xy + yy’ = x (c) xyz + x’y + xyz’ = xy(z + z’) + x’y = xy + x’y = y (d) (A + B)’(A’ + B’)’ = (A’B’)(A B) = (A’B’)(BA) = A’(B’B)A = 0 (e) (a + b + c’)(a’b’ + c) = aa’b’ + ac + ba’b’ + bc + c’a’b’ + c’c = ac + bc +a’b’c’ (f) a’bc + abc’ + abc + a’bc’ = a’b(c + c’) + ab(c + c’) = a’b + ab = (a’ + a)b = b 2.3(a) ABC + A’B + ABC’ = AB + A’B = BDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual 10 (b) x’yz + xz = (x’y + x)z = z(x + x’)(x + y) = z(x + y) (c) (x + y)’(x’ + y’) = x’y’(x’ + y’) = x’y’ (d) xy + x(wz + wz’) = x(y +wz + wz’) = x(w + y) (e) (BC’ + A’D)(AB’ + CD’) = BC’AB’ + BC’CD’ + A’DAB’ + A’DCD’ = 0 (f) (a’ + c’)(a + b’ + c’) = a’a + a’b’ + a’c’ + c’a + c’b’ + c’c’ = a’b’ + a’c’ + ac’ + b’c’ = c’ + b’(a’ + c’) = c’ + b’c’ + a’b’ = c’ + a’b’ 2.4(a) A’C’ + ABC + AC’ = C’ + ABC = (C + C’)(C’ + AB) = AB + C’ (b) (x’y’ + z)’ + z + xy + wz = (x’y’)’z’ + z + xy + wz =[ (x + y)z’ + z] + xy + wz = = (z + z’)(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z (c) A’B(D’ + C’D) + B(A + A’CD) = B(A’D’ + A’C’D + A + A’CD) = B(A’D’ + A + A’D(C + C’) = B(A + A’(D’ + D)) = B(A + A’) = B (d) (A’ + C)(A’ + C’)(A + B + C’D) = (A’ + CC’)(A + B + C’D) = A’(A + B + C’D) = AA’ + A’B + A’C’D = A’(B + C’D) (e) ABC’D + A’BD + ABCD = AB(C + C’)D + A’BD = ABD + A’BD = BD 2.5(a) xyFsimplifiedF (b) xy FsimplifiedF(c)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-ManualFull file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual xyz FsimplifiedF(d) AB0 FsimplifiedF(e) xyz FsimplifiedF(f)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual11 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual xyzFFsimplified2.6(a) ABCFFsimplified(b) xyzFFsimplified(c) xyFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual12 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (d) wxyzFFsimplified(e) ABCD Fsimplified = 0F(f) wxyzFFsimplified2.7(a) ABCDFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual13 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (b) wxyzFFsimplified(c) ABCDFFsimplified(d) ABCDFFsimplifiedDigital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual14 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (e) ABCDFFsimplified 2.8 F’ = (wx + yz)’ = (wx)’(yz)’ = (w’ + x’)(y’ + z’) FF’ = wx(w’ + x’)(y’ + z’) + yz(w’ + x’)(y’ + z’) = 0 F + F’ = wx + yz + (wx + yz)’ = A + A’ = 1 with A = wx + yz 2.9(a) F’ = (xy’ + x’y)’ = (xy’)’(x’y)’ = (x’ + y)(x + y’) = xy + x’y’ (b) F’ = [(a + c) (a + b’)(a’ + b + c’)]’ = (a + c)’ + (a + b’)’ + (a’ + b + c’)’ =a’c’ + a’b + ab’c (c) F’ = [z + z’(v’w + xy)]’ = z’[z’(v’w + xy)]’ = z’[z’v’w + xyz’]’ = z’[(z’v’w)’(xyz’)’] = z’[(z + v + w’) +( x’ + y’ + z)] = z’z + z’v + z’w’ + z’x’ + z’y’ +z’ z = z’(v + w’ + x’ + y’) 2.10 2.11(a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i) (b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j (a) F(x, y, z) = Σ(1, 4, 5, 6, 7) (b) F(a, b, c) = Σ(0, 2, 3, 7) F = xy + xy’ + y’z 2.12F = bc + a’c’xyzFabcF000 001 010 011 100 101 110 1110 1 0 0 1 1 1 1000 001 010 011 100 101 110 1111 0 1 1 0 0 0 1A = 1011_0001 B = 1010_1100Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual15 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual (a) (b) (c) (d) (e) 2.13A AND B = 1010_0000 A OR B = 1011_1101 A XOR B = 0001_1101 NOT A = 0100_1110 NOT B = 0101_0011(a) uxyz(u + x’) Y = [(u + x’)(y’ + z)] (y’ + z)(b) u x yx Y = (u xor y)’ + x (u xor y)’(c) uxy z(u’+ x’) Y = (u’+ x’)(y + z’) (y + z’)(d) u x yzu(x xor z) Y = u(x xor z) + y’y’ (e) u x y zu yzY = u + yz +uxyuxy(f)Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual16 Full file at https://testbankuniv.eu/Digital-Design-5th-Edition-Mano-Solutions-Manual u xyY = u + x + x’(u + y’) x’(u + y’) (u + y’)2.14(a) xyzF =xy + x’y’ + y’z(b) xyzF = xy + x’y’ + y’z = (x’ + y’)’ + (x + y)’ + (y + z
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